I. Field of Invention
This invention relates generally to apparatus for optimizing the performance of energy consuming machines or systems and more specifically to an improved digital electronic device for sampling the effect on the performance of such a machine or system of an incremental change in the setting of a control parameter and using the resulting information resulting from the sampling process to adjust the setting in a way which tends to optimize the system performance.
II. Description of Prior Art
In the Schweitzer et al. U.S. Pat. No. 4,026,251 there is described an optimizing control system of which the present invention is deemed to be an improvement. In accordance with the teachings of the aforementioned Schweitzer et al Patent, an electronic oscillator is provided for producing "dither" pulses of a relatively long duration and low repetition rate. These dither pulses are applied to a suitable transducer such as an electric motor or solenoid which, in turn, is used to produce a slight variation in a system control parameter of a machine. Coupled to the output of the machine is an electrical pulse generating device (termed a "celsig") which produces pulses of a relatively high rate compared to the rate at which the dither pulses are produced by the oscillator. These high frequency pulses are produced at a rate which is directly proportional to the output of the machine. The dither pulses are also applied to timing networks which effectively divide the dither pulses into segments. The output of the timing networks are coupled through coincident circuits (AND gates) to the input terminals of an up-down pulse counting network. Applied to second input of these AND gates are the high frequency pulses whose rate is proportional to the instantaneous output of the machine. Thus, during a first portion of a dither cycle, the counter network counts up the number of high frequency pulses received and subsequently, during a second equal portion of the dither cycle, the counter network is decremented by the number of high frequency pulses received during this known second time interval. If the count passes through zero, it is known that the system output has increased as a result of the dithering of the controlling parameter. However, if the count remains positive during the countdown period, it is known that the engine output has decreased. Thus, the counter serves to develop the algebraic difference of the high rate pulses (which are proportional to the machine or system output) which occur during successive intervals of a dither pulse. The output from the up-down counter is coupled through a logic device including flip-flops and gates to a suitable transducer whose output is used to either increase or decrease the parameter setting so as to optimize the machine performance.
In the aforementioned Schweitzer et al Patent, it was necessary that the dither oscillator 53 therein remain constant in frequency in that the RC delay times of the one-shot circuits 66 and 74 were used to establish the count-up and count-down periods of the counter 108. Because the periods during which the one-shot circuits are active are essentially fixed for any given setting of the RC time constant, it can be seen that variations in the frequency of the dither oscillator 53 can result in somewhat erratic operation in that the initiation of the one-shot circuit period is related to the frequency of the dither oscillator whereas the termination of the period is a function of the fixed RC parameters. Then too, for reliable operation it is required that precision, and therefore expensive, components be used in the timing network on the one-shot circuit 66 and 74.
The circuit arrangements of the present invention obviate these problems by completely eliminating the analog components i.e., the one-shot circuit and their associated RC time delay networks. Thus, in accordance with the teachings of the present invention, the system is independent of any changes in clock frequency and the accuracy of the system remains fixed, independent of any such clock frequency changes.
In addition to the foregoing improvement in accuracy, the system of the present invention is also designed to permit the selective insertion of differing bias values. As was described in the aforereferenced Schweitzer et al Patent, if for any reason optimum setting is not desired, for instance because of some restraints or considerations make its use objectionable, the technique of biasing can deliver near optimum settings, off optimum by a predetermined amount.
In the circuit of FIG. 3 of the prior art Schweitzer Patent, the advance periods and retard periods are divided into two equal segments each, and in the unbiased case the counting is reversed at the midpoint of each segment. However, if the segments are made unequal, the upcounts and downcounts will be different. To accomplish biasing, the periods that the two one-shotcircuits 66 and 74 were active as determined by their associated RC time constant networks were made unequal. Thus, a preference could be given to the upcount portion of a dither cycle or to the downcount portion of this cycle. Again, establishing the desired bias was a function of analog components which added to the cost and instability of the system. It is significant to note that whereas the prior art used the adjustment of two numbers in order to achieve biasing, the present invention allows biasing through the selection of only one such number, again simplifying the circuitry.